/*
 * Copyright (c) Huawei Technologies Co., Ltd. 2019-2022. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
 * only version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * Description:
 * Author: huawei
 * Create: 2019-10-15
 */

#ifndef HILINK_RX_CSR_REG_OFFSET_FIELD_H
#define HILINK_RX_CSR_REG_OFFSET_FIELD_H

#define RX_CSR_0_BIT3_LEN 3
#define RX_CSR_0_BIT3_OFFSET 3
#define RX_CSR_0_BIT0_LEN 3
#define RX_CSR_0_BIT0_OFFSET 0

#define RX_CSR_1_BIT16_LEN 16
#define RX_CSR_1_BIT16_OFFSET 16
#define RX_CSR_1_BIT0_LEN 16
#define RX_CSR_1_BIT0_OFFSET 0

#define RX_CSR_2_BIT28_LEN 3
#define RX_CSR_2_BIT28_OFFSET 28
#define RX_CSR_2_BIT14_LEN 14
#define RX_CSR_2_BIT14_OFFSET 14
#define RX_CSR_2_BIT0_LEN 14
#define RX_CSR_2_BIT0_OFFSET 0

#define RX_CSR_3_BIT14_LEN 1
#define RX_CSR_3_BIT14_OFFSET 14
#define RX_CSR_3_BIT0_LEN 14
#define RX_CSR_3_BIT0_OFFSET 0

#define RX_CSR_4_BIT0_LEN 32
#define RX_CSR_4_BIT0_OFFSET 0

#define RX_CSR_5_BIT0_LEN 32
#define RX_CSR_5_BIT0_OFFSET 0

#define RX_CSR_6_BIT15_LEN 17
#define RX_CSR_6_BIT15_OFFSET 15
#define RX_CSR_6_BIT0_LEN 14
#define RX_CSR_6_BIT0_OFFSET 0

#define RX_CSR_7_BIT22_LEN 10
#define RX_CSR_7_BIT22_OFFSET 22
#define RX_CSR_7_BIT17_LEN 4
#define RX_CSR_7_BIT17_OFFSET 17
#define RX_CSR_7_BIT16_LEN 1
#define RX_CSR_7_BIT16_OFFSET 16
#define RX_CSR_7_BIT8_LEN 8
#define RX_CSR_7_BIT8_OFFSET 8
#define RX_CSR_7_BIT0_LEN 2
#define RX_CSR_7_BIT0_OFFSET 0

#define RX_CSR_8_BIT14_LEN 14
#define RX_CSR_8_BIT14_OFFSET 14
#define RX_CSR_8_BIT0_LEN 14
#define RX_CSR_8_BIT0_OFFSET 0

#define RX_CSR_9_BIT14_LEN 14
#define RX_CSR_9_BIT14_OFFSET 14
#define RX_CSR_9_BIT0_LEN 14
#define RX_CSR_9_BIT0_OFFSET 0

#define RX_CSR_10_BIT0_LEN 32
#define RX_CSR_10_BIT0_OFFSET 0

#define RX_CSR_11_BIT0_LEN 32
#define RX_CSR_11_BIT0_OFFSET 0

#define RX_CSR_12_BIT20_LEN 1
#define RX_CSR_12_BIT20_OFFSET 20
#define RX_CSR_12_BIT19_LEN 1
#define RX_CSR_12_BIT19_OFFSET 19
#define RX_CSR_12_BIT18_LEN 1
#define RX_CSR_12_BIT18_OFFSET 18
#define RX_CSR_12_BIT14_LEN 4
#define RX_CSR_12_BIT14_OFFSET 14
#define RX_CSR_12_BIT0_LEN 14
#define RX_CSR_12_BIT0_OFFSET 0

#define RX_CSR_13_BIT24_LEN 1
#define RX_CSR_13_BIT24_OFFSET 24
#define RX_CSR_13_BIT23_LEN 1
#define RX_CSR_13_BIT23_OFFSET 23
#define RX_CSR_13_BIT22_LEN 1
#define RX_CSR_13_BIT22_OFFSET 22
#define RX_CSR_13_BIT21_LEN 1
#define RX_CSR_13_BIT21_OFFSET 21
#define RX_CSR_13_BIT20_LEN 1
#define RX_CSR_13_BIT20_OFFSET 20
#define RX_CSR_13_BIT19_LEN 1
#define RX_CSR_13_BIT19_OFFSET 19
#define RX_CSR_13_BIT18_LEN 1
#define RX_CSR_13_BIT18_OFFSET 18
#define RX_CSR_13_BIT17_LEN 1
#define RX_CSR_13_BIT17_OFFSET 17
#define RX_CSR_13_BIT16_LEN 1
#define RX_CSR_13_BIT16_OFFSET 16
#define RX_CSR_13_BIT12_LEN 4
#define RX_CSR_13_BIT12_OFFSET 12
#define RX_CSR_13_BIT8_LEN 4
#define RX_CSR_13_BIT8_OFFSET 8
#define RX_CSR_13_BIT4_LEN 4
#define RX_CSR_13_BIT4_OFFSET 4
#define RX_CSR_13_BIT0_LEN 4
#define RX_CSR_13_BIT0_OFFSET 0

#define RX_CSR_14_BIT16_LEN 3
#define RX_CSR_14_BIT16_OFFSET 16
#define RX_CSR_14_BIT15_LEN 1
#define RX_CSR_14_BIT15_OFFSET 15
#define RX_CSR_14_BIT14_LEN 1
#define RX_CSR_14_BIT14_OFFSET 14
#define RX_CSR_14_BIT0_LEN 14
#define RX_CSR_14_BIT0_OFFSET 0

#define RX_CSR_15_BIT28_LEN 3
#define RX_CSR_15_BIT28_OFFSET 28
#define RX_CSR_15_BIT22_LEN 6
#define RX_CSR_15_BIT22_OFFSET 22
#define RX_CSR_15_BIT18_LEN 4
#define RX_CSR_15_BIT18_OFFSET 18
#define RX_CSR_15_BIT17_LEN 1
#define RX_CSR_15_BIT17_OFFSET 17
#define RX_CSR_15_BIT1_LEN 16
#define RX_CSR_15_BIT1_OFFSET 1
#define RX_CSR_15_BIT0_LEN 1
#define RX_CSR_15_BIT0_OFFSET 0

#define RX_CSR_16_BIT0_LEN 32
#define RX_CSR_16_BIT0_OFFSET 0

#define RX_CSR_17_BIT0_LEN 32
#define RX_CSR_17_BIT0_OFFSET 0

#define RX_CSR_18_BIT30_LEN 1
#define RX_CSR_18_BIT30_OFFSET 30
#define RX_CSR_18_BIT29_LEN 1
#define RX_CSR_18_BIT29_OFFSET 29
#define RX_CSR_18_BIT28_LEN 1
#define RX_CSR_18_BIT28_OFFSET 28
#define RX_CSR_18_BIT27_LEN 1
#define RX_CSR_18_BIT27_OFFSET 27
#define RX_CSR_18_BIT18_LEN 9
#define RX_CSR_18_BIT18_OFFSET 18
#define RX_CSR_18_BIT14_LEN 4
#define RX_CSR_18_BIT14_OFFSET 14
#define RX_CSR_18_BIT13_LEN 1
#define RX_CSR_18_BIT13_OFFSET 13
#define RX_CSR_18_BIT12_LEN 1
#define RX_CSR_18_BIT12_OFFSET 12
#define RX_CSR_18_BIT8_LEN 4
#define RX_CSR_18_BIT8_OFFSET 8
#define RX_CSR_18_BIT7_LEN 1
#define RX_CSR_18_BIT7_OFFSET 7
#define RX_CSR_18_BIT6_LEN 1
#define RX_CSR_18_BIT6_OFFSET 6
#define RX_CSR_18_BIT2_LEN 4
#define RX_CSR_18_BIT2_OFFSET 2
#define RX_CSR_18_BIT1_LEN 1
#define RX_CSR_18_BIT1_OFFSET 1
#define RX_CSR_18_BIT0_LEN 1
#define RX_CSR_18_BIT0_OFFSET 0

#define RX_CSR_19_BIT2_LEN 2
#define RX_CSR_19_BIT2_OFFSET 2
#define RX_CSR_19_BIT0_LEN 2
#define RX_CSR_19_BIT0_OFFSET 0

#define RX_CSR_21_BIT18_LEN 1
#define RX_CSR_21_BIT18_OFFSET 18
#define RX_CSR_21_BIT17_LEN 1
#define RX_CSR_21_BIT17_OFFSET 17
#define RX_CSR_21_BIT16_LEN 1
#define RX_CSR_21_BIT16_OFFSET 16
#define RX_CSR_21_BIT15_LEN 1
#define RX_CSR_21_BIT15_OFFSET 15
#define RX_CSR_21_BIT14_LEN 1
#define RX_CSR_21_BIT14_OFFSET 14
#define RX_CSR_21_BIT13_LEN 1
#define RX_CSR_21_BIT13_OFFSET 13
#define RX_CSR_21_BIT12_LEN 1
#define RX_CSR_21_BIT12_OFFSET 12
#define RX_CSR_21_BIT11_LEN 1
#define RX_CSR_21_BIT11_OFFSET 11
#define RX_CSR_21_BIT10_LEN 1
#define RX_CSR_21_BIT10_OFFSET 10
#define RX_CSR_21_BIT9_LEN 1
#define RX_CSR_21_BIT9_OFFSET 9
#define RX_CSR_21_BIT8_LEN 1
#define RX_CSR_21_BIT8_OFFSET 8
#define RX_CSR_21_BIT7_LEN 1
#define RX_CSR_21_BIT7_OFFSET 7
#define RX_CSR_21_BIT6_LEN 1
#define RX_CSR_21_BIT6_OFFSET 6
#define RX_CSR_21_BIT5_LEN 1
#define RX_CSR_21_BIT5_OFFSET 5
#define RX_CSR_21_BIT4_LEN 1
#define RX_CSR_21_BIT4_OFFSET 4
#define RX_CSR_21_BIT3_LEN 1
#define RX_CSR_21_BIT3_OFFSET 3
#define RX_CSR_21_BIT2_LEN 1
#define RX_CSR_21_BIT2_OFFSET 2
#define RX_CSR_21_BIT1_LEN 1
#define RX_CSR_21_BIT1_OFFSET 1
#define RX_CSR_21_BIT0_LEN 1
#define RX_CSR_21_BIT0_OFFSET 0

#define RX_CSR_22_BIT7_LEN 1
#define RX_CSR_22_BIT7_OFFSET 7
#define RX_CSR_22_BIT6_LEN 1
#define RX_CSR_22_BIT6_OFFSET 6
#define RX_CSR_22_BIT5_LEN 1
#define RX_CSR_22_BIT5_OFFSET 5
#define RX_CSR_22_BIT4_LEN 1
#define RX_CSR_22_BIT4_OFFSET 4
#define RX_CSR_22_BIT3_LEN 1
#define RX_CSR_22_BIT3_OFFSET 3
#define RX_CSR_22_BIT2_LEN 1
#define RX_CSR_22_BIT2_OFFSET 2
#define RX_CSR_22_BIT1_LEN 1
#define RX_CSR_22_BIT1_OFFSET 1
#define RX_CSR_22_BIT0_LEN 1
#define RX_CSR_22_BIT0_OFFSET 0

#define RX_CSR_23_BIT23_LEN 1
#define RX_CSR_23_BIT23_OFFSET 23
#define RX_CSR_23_BIT22_LEN 1
#define RX_CSR_23_BIT22_OFFSET 22
#define RX_CSR_23_BIT21_LEN 1
#define RX_CSR_23_BIT21_OFFSET 21
#define RX_CSR_23_BIT16_LEN 5
#define RX_CSR_23_BIT16_OFFSET 16
#define RX_CSR_23_BIT12_LEN 4
#define RX_CSR_23_BIT12_OFFSET 12
#define RX_CSR_23_BIT1_LEN 11
#define RX_CSR_23_BIT1_OFFSET 1
#define RX_CSR_23_BIT0_LEN 1
#define RX_CSR_23_BIT0_OFFSET 0

#define RX_CSR_24_BIT31_LEN 1
#define RX_CSR_24_BIT31_OFFSET 31
#define RX_CSR_24_BIT30_LEN 1
#define RX_CSR_24_BIT30_OFFSET 30
#define RX_CSR_24_BIT29_LEN 1
#define RX_CSR_24_BIT29_OFFSET 29
#define RX_CSR_24_BIT28_LEN 1
#define RX_CSR_24_BIT28_OFFSET 28
#define RX_CSR_24_BIT27_LEN 1
#define RX_CSR_24_BIT27_OFFSET 27
#define RX_CSR_24_BIT23_LEN 4
#define RX_CSR_24_BIT23_OFFSET 23
#define RX_CSR_24_BIT14_LEN 9
#define RX_CSR_24_BIT14_OFFSET 14
#define RX_CSR_24_BIT13_LEN 1
#define RX_CSR_24_BIT13_OFFSET 13
#define RX_CSR_24_BIT12_LEN 1
#define RX_CSR_24_BIT12_OFFSET 12
#define RX_CSR_24_BIT11_LEN 1
#define RX_CSR_24_BIT11_OFFSET 11
#define RX_CSR_24_BIT10_LEN 1
#define RX_CSR_24_BIT10_OFFSET 10
#define RX_CSR_24_BIT9_LEN 1
#define RX_CSR_24_BIT9_OFFSET 9
#define RX_CSR_24_BIT8_LEN 1
#define RX_CSR_24_BIT8_OFFSET 8
#define RX_CSR_24_BIT6_LEN 2
#define RX_CSR_24_BIT6_OFFSET 6
#define RX_CSR_24_BIT3_LEN 3
#define RX_CSR_24_BIT3_OFFSET 3
#define RX_CSR_24_BIT0_LEN 3
#define RX_CSR_24_BIT0_OFFSET 0

#define RX_CSR_25_BIT24_LEN 4
#define RX_CSR_25_BIT24_OFFSET 24
#define RX_CSR_25_BIT13_LEN 11
#define RX_CSR_25_BIT13_OFFSET 13
#define RX_CSR_25_BIT9_LEN 4
#define RX_CSR_25_BIT9_OFFSET 9
#define RX_CSR_25_BIT0_LEN 9
#define RX_CSR_25_BIT0_OFFSET 0

#define RX_CSR_26_BIT3_LEN 1
#define RX_CSR_26_BIT3_OFFSET 3
#define RX_CSR_26_BIT2_LEN 1
#define RX_CSR_26_BIT2_OFFSET 2
#define RX_CSR_26_BIT1_LEN 1
#define RX_CSR_26_BIT1_OFFSET 1
#define RX_CSR_26_BIT0_LEN 1
#define RX_CSR_26_BIT0_OFFSET 0

#define RX_CSR_27_BIT13_LEN 1
#define RX_CSR_27_BIT13_OFFSET 13
#define RX_CSR_27_BIT12_LEN 1
#define RX_CSR_27_BIT12_OFFSET 12
#define RX_CSR_27_BIT11_LEN 1
#define RX_CSR_27_BIT11_OFFSET 11
#define RX_CSR_27_BIT10_LEN 1
#define RX_CSR_27_BIT10_OFFSET 10
#define RX_CSR_27_BIT9_LEN 1
#define RX_CSR_27_BIT9_OFFSET 9
#define RX_CSR_27_BIT8_LEN 1
#define RX_CSR_27_BIT8_OFFSET 8
#define RX_CSR_27_BIT7_LEN 1
#define RX_CSR_27_BIT7_OFFSET 7
#define RX_CSR_27_BIT6_LEN 1
#define RX_CSR_27_BIT6_OFFSET 6
#define RX_CSR_27_BIT5_LEN 1
#define RX_CSR_27_BIT5_OFFSET 5
#define RX_CSR_27_BIT4_LEN 1
#define RX_CSR_27_BIT4_OFFSET 4
#define RX_CSR_27_BIT3_LEN 1
#define RX_CSR_27_BIT3_OFFSET 3
#define RX_CSR_27_BIT2_LEN 1
#define RX_CSR_27_BIT2_OFFSET 2
#define RX_CSR_27_BIT0_LEN 2
#define RX_CSR_27_BIT0_OFFSET 0

#define RX_CSR_28_BIT19_LEN 3
#define RX_CSR_28_BIT19_OFFSET 19
#define RX_CSR_28_BIT11_LEN 8
#define RX_CSR_28_BIT11_OFFSET 11
#define RX_CSR_28_BIT4_LEN 7
#define RX_CSR_28_BIT4_OFFSET 4
#define RX_CSR_28_BIT3_LEN 1
#define RX_CSR_28_BIT3_OFFSET 3
#define RX_CSR_28_BIT2_LEN 1
#define RX_CSR_28_BIT2_OFFSET 2
#define RX_CSR_28_BIT0_LEN 2
#define RX_CSR_28_BIT0_OFFSET 0

#define RX_CSR_29_BIT20_LEN 12
#define RX_CSR_29_BIT20_OFFSET 20
#define RX_CSR_29_BIT0_LEN 20
#define RX_CSR_29_BIT0_OFFSET 0

#define RX_CSR_30_BIT15_LEN 16
#define RX_CSR_30_BIT15_OFFSET 15
#define RX_CSR_30_BIT14_LEN 1
#define RX_CSR_30_BIT14_OFFSET 14
#define RX_CSR_30_BIT9_LEN 5
#define RX_CSR_30_BIT9_OFFSET 9
#define RX_CSR_30_BIT4_LEN 5
#define RX_CSR_30_BIT4_OFFSET 4
#define RX_CSR_30_BIT3_LEN 1
#define RX_CSR_30_BIT3_OFFSET 3
#define RX_CSR_30_BIT0_LEN 3
#define RX_CSR_30_BIT0_OFFSET 0

#define RX_CSR_31_BIT22_LEN 6
#define RX_CSR_31_BIT22_OFFSET 22
#define RX_CSR_31_BIT10_LEN 12
#define RX_CSR_31_BIT10_OFFSET 10
#define RX_CSR_31_BIT9_LEN 1
#define RX_CSR_31_BIT9_OFFSET 9
#define RX_CSR_31_BIT8_LEN 1
#define RX_CSR_31_BIT8_OFFSET 8
#define RX_CSR_31_BIT7_LEN 1
#define RX_CSR_31_BIT7_OFFSET 7
#define RX_CSR_31_BIT6_LEN 1
#define RX_CSR_31_BIT6_OFFSET 6
#define RX_CSR_31_BIT3_LEN 3
#define RX_CSR_31_BIT3_OFFSET 3
#define RX_CSR_31_BIT0_LEN 3
#define RX_CSR_31_BIT0_OFFSET 0

#define RX_CSR_32_BIT30_LEN 1
#define RX_CSR_32_BIT30_OFFSET 30
#define RX_CSR_32_BIT29_LEN 1
#define RX_CSR_32_BIT29_OFFSET 29
#define RX_CSR_32_BIT28_LEN 1
#define RX_CSR_32_BIT28_OFFSET 28
#define RX_CSR_32_BIT27_LEN 1
#define RX_CSR_32_BIT27_OFFSET 27
#define RX_CSR_32_BIT26_LEN 1
#define RX_CSR_32_BIT26_OFFSET 26
#define RX_CSR_32_BIT18_LEN 8
#define RX_CSR_32_BIT18_OFFSET 18
#define RX_CSR_32_BIT6_LEN 12
#define RX_CSR_32_BIT6_OFFSET 6
#define RX_CSR_32_BIT3_LEN 3
#define RX_CSR_32_BIT3_OFFSET 3
#define RX_CSR_32_BIT0_LEN 3
#define RX_CSR_32_BIT0_OFFSET 0

#define RX_CSR_33_BIT17_LEN 1
#define RX_CSR_33_BIT17_OFFSET 17
#define RX_CSR_33_BIT16_LEN 1
#define RX_CSR_33_BIT16_OFFSET 16
#define RX_CSR_33_BIT9_LEN 7
#define RX_CSR_33_BIT9_OFFSET 9
#define RX_CSR_33_BIT8_LEN 1
#define RX_CSR_33_BIT8_OFFSET 8
#define RX_CSR_33_BIT0_LEN 8
#define RX_CSR_33_BIT0_OFFSET 0

#define RX_CSR_34_BIT24_LEN 1
#define RX_CSR_34_BIT24_OFFSET 24
#define RX_CSR_34_BIT21_LEN 3
#define RX_CSR_34_BIT21_OFFSET 21
#define RX_CSR_34_BIT14_LEN 7
#define RX_CSR_34_BIT14_OFFSET 14
#define RX_CSR_34_BIT7_LEN 7
#define RX_CSR_34_BIT7_OFFSET 7
#define RX_CSR_34_BIT0_LEN 7
#define RX_CSR_34_BIT0_OFFSET 0

#define RX_CSR_35_BIT22_LEN 6
#define RX_CSR_35_BIT22_OFFSET 22
#define RX_CSR_35_BIT16_LEN 6
#define RX_CSR_35_BIT16_OFFSET 16
#define RX_CSR_35_BIT10_LEN 6
#define RX_CSR_35_BIT10_OFFSET 10
#define RX_CSR_35_BIT2_LEN 8
#define RX_CSR_35_BIT2_OFFSET 2
#define RX_CSR_35_BIT1_LEN 1
#define RX_CSR_35_BIT1_OFFSET 1
#define RX_CSR_35_BIT0_LEN 1
#define RX_CSR_35_BIT0_OFFSET 0

#define RX_CSR_36_BIT31_LEN 1
#define RX_CSR_36_BIT31_OFFSET 31
#define RX_CSR_36_BIT27_LEN 4
#define RX_CSR_36_BIT27_OFFSET 27
#define RX_CSR_36_BIT26_LEN 1
#define RX_CSR_36_BIT26_OFFSET 26
#define RX_CSR_36_BIT25_LEN 1
#define RX_CSR_36_BIT25_OFFSET 25
#define RX_CSR_36_BIT5_LEN 20
#define RX_CSR_36_BIT5_OFFSET 5
#define RX_CSR_36_BIT4_LEN 1
#define RX_CSR_36_BIT4_OFFSET 4
#define RX_CSR_36_BIT0_LEN 4
#define RX_CSR_36_BIT0_OFFSET 0

#define RX_CSR_37_BIT13_LEN 16
#define RX_CSR_37_BIT13_OFFSET 13
#define RX_CSR_37_BIT8_LEN 5
#define RX_CSR_37_BIT8_OFFSET 8
#define RX_CSR_37_BIT7_LEN 1
#define RX_CSR_37_BIT7_OFFSET 7
#define RX_CSR_37_BIT6_LEN 1
#define RX_CSR_37_BIT6_OFFSET 6
#define RX_CSR_37_BIT0_LEN 6
#define RX_CSR_37_BIT0_OFFSET 0

#define RX_CSR_38_BIT11_LEN 1
#define RX_CSR_38_BIT11_OFFSET 11
#define RX_CSR_38_BIT10_LEN 1
#define RX_CSR_38_BIT10_OFFSET 10
#define RX_CSR_38_BIT9_LEN 1
#define RX_CSR_38_BIT9_OFFSET 9
#define RX_CSR_38_BIT8_LEN 1
#define RX_CSR_38_BIT8_OFFSET 8
#define RX_CSR_38_BIT7_LEN 1
#define RX_CSR_38_BIT7_OFFSET 7
#define RX_CSR_38_BIT5_LEN 2
#define RX_CSR_38_BIT5_OFFSET 5
#define RX_CSR_38_BIT1_LEN 4
#define RX_CSR_38_BIT1_OFFSET 1
#define RX_CSR_38_BIT0_LEN 1
#define RX_CSR_38_BIT0_OFFSET 0

#define RX_CSR_39_BIT6_LEN 1
#define RX_CSR_39_BIT6_OFFSET 6
#define RX_CSR_39_BIT3_LEN 3
#define RX_CSR_39_BIT3_OFFSET 3
#define RX_CSR_39_BIT1_LEN 2
#define RX_CSR_39_BIT1_OFFSET 1
#define RX_CSR_39_BIT0_LEN 1
#define RX_CSR_39_BIT0_OFFSET 0

#define RX_CSR_41_BIT31_LEN 1
#define RX_CSR_41_BIT31_OFFSET 31
#define RX_CSR_41_BIT30_LEN 1
#define RX_CSR_41_BIT30_OFFSET 30
#define RX_CSR_41_BIT29_LEN 1
#define RX_CSR_41_BIT29_OFFSET 29
#define RX_CSR_41_BIT21_LEN 8
#define RX_CSR_41_BIT21_OFFSET 21
#define RX_CSR_41_BIT13_LEN 8
#define RX_CSR_41_BIT13_OFFSET 13
#define RX_CSR_41_BIT7_LEN 6
#define RX_CSR_41_BIT7_OFFSET 7
#define RX_CSR_41_BIT3_LEN 4
#define RX_CSR_41_BIT3_OFFSET 3
#define RX_CSR_41_BIT0_LEN 3
#define RX_CSR_41_BIT0_OFFSET 0

#define RX_CSR_42_BIT18_LEN 1
#define RX_CSR_42_BIT18_OFFSET 18
#define RX_CSR_42_BIT17_LEN 1
#define RX_CSR_42_BIT17_OFFSET 17
#define RX_CSR_42_BIT16_LEN 1
#define RX_CSR_42_BIT16_OFFSET 16
#define RX_CSR_42_BIT12_LEN 4
#define RX_CSR_42_BIT12_OFFSET 12
#define RX_CSR_42_BIT8_LEN 4
#define RX_CSR_42_BIT8_OFFSET 8
#define RX_CSR_42_BIT4_LEN 4
#define RX_CSR_42_BIT4_OFFSET 4
#define RX_CSR_42_BIT0_LEN 4
#define RX_CSR_42_BIT0_OFFSET 0

#define RX_CSR_43_BIT27_LEN 1
#define RX_CSR_43_BIT27_OFFSET 27
#define RX_CSR_43_BIT26_LEN 1
#define RX_CSR_43_BIT26_OFFSET 26
#define RX_CSR_43_BIT25_LEN 1
#define RX_CSR_43_BIT25_OFFSET 25
#define RX_CSR_43_BIT24_LEN 1
#define RX_CSR_43_BIT24_OFFSET 24
#define RX_CSR_43_BIT16_LEN 8
#define RX_CSR_43_BIT16_OFFSET 16
#define RX_CSR_43_BIT7_LEN 9
#define RX_CSR_43_BIT7_OFFSET 7
#define RX_CSR_43_BIT0_LEN 7
#define RX_CSR_43_BIT0_OFFSET 0

#define RX_CSR_44_BIT25_LEN 7
#define RX_CSR_44_BIT25_OFFSET 25
#define RX_CSR_44_BIT16_LEN 9
#define RX_CSR_44_BIT16_OFFSET 16
#define RX_CSR_44_BIT12_LEN 4
#define RX_CSR_44_BIT12_OFFSET 12
#define RX_CSR_44_BIT9_LEN 3
#define RX_CSR_44_BIT9_OFFSET 9
#define RX_CSR_44_BIT6_LEN 3
#define RX_CSR_44_BIT6_OFFSET 6
#define RX_CSR_44_BIT3_LEN 3
#define RX_CSR_44_BIT3_OFFSET 3
#define RX_CSR_44_BIT1_LEN 2
#define RX_CSR_44_BIT1_OFFSET 1
#define RX_CSR_44_BIT0_LEN 1
#define RX_CSR_44_BIT0_OFFSET 0

#define RX_CSR_45_BIT23_LEN 5
#define RX_CSR_45_BIT23_OFFSET 23
#define RX_CSR_45_BIT0_LEN 23
#define RX_CSR_45_BIT0_OFFSET 0

#define RX_CSR_46_BIT27_LEN 5
#define RX_CSR_46_BIT27_OFFSET 27
#define RX_CSR_46_BIT23_LEN 4
#define RX_CSR_46_BIT23_OFFSET 23
#define RX_CSR_46_BIT22_LEN 1
#define RX_CSR_46_BIT22_OFFSET 22
#define RX_CSR_46_BIT21_LEN 1
#define RX_CSR_46_BIT21_OFFSET 21
#define RX_CSR_46_BIT17_LEN 4
#define RX_CSR_46_BIT17_OFFSET 17
#define RX_CSR_46_BIT16_LEN 1
#define RX_CSR_46_BIT16_OFFSET 16
#define RX_CSR_46_BIT15_LEN 1
#define RX_CSR_46_BIT15_OFFSET 15
#define RX_CSR_46_BIT14_LEN 1
#define RX_CSR_46_BIT14_OFFSET 14
#define RX_CSR_46_BIT5_LEN 9
#define RX_CSR_46_BIT5_OFFSET 5
#define RX_CSR_46_BIT4_LEN 1
#define RX_CSR_46_BIT4_OFFSET 4
#define RX_CSR_46_BIT3_LEN 1
#define RX_CSR_46_BIT3_OFFSET 3
#define RX_CSR_46_BIT2_LEN 1
#define RX_CSR_46_BIT2_OFFSET 2
#define RX_CSR_46_BIT1_LEN 1
#define RX_CSR_46_BIT1_OFFSET 1
#define RX_CSR_46_BIT0_LEN 1
#define RX_CSR_46_BIT0_OFFSET 0

#define RX_CSR_47_BIT24_LEN 1
#define RX_CSR_47_BIT24_OFFSET 24
#define RX_CSR_47_BIT23_LEN 1
#define RX_CSR_47_BIT23_OFFSET 23
#define RX_CSR_47_BIT20_LEN 3
#define RX_CSR_47_BIT20_OFFSET 20
#define RX_CSR_47_BIT19_LEN 1
#define RX_CSR_47_BIT19_OFFSET 19
#define RX_CSR_47_BIT18_LEN 1
#define RX_CSR_47_BIT18_OFFSET 18
#define RX_CSR_47_BIT9_LEN 9
#define RX_CSR_47_BIT9_OFFSET 9
#define RX_CSR_47_BIT0_LEN 9
#define RX_CSR_47_BIT0_OFFSET 0

#define RX_CSR_48_BIT31_LEN 1
#define RX_CSR_48_BIT31_OFFSET 31
#define RX_CSR_48_BIT0_LEN 31
#define RX_CSR_48_BIT0_OFFSET 0

#define RX_CSR_49_BIT9_LEN 9
#define RX_CSR_49_BIT9_OFFSET 9
#define RX_CSR_49_BIT0_LEN 9
#define RX_CSR_49_BIT0_OFFSET 0

#define RX_CSR_50_BIT16_LEN 16
#define RX_CSR_50_BIT16_OFFSET 16
#define RX_CSR_50_BIT0_LEN 16
#define RX_CSR_50_BIT0_OFFSET 0

#define RX_CSR_51_BIT16_LEN 16
#define RX_CSR_51_BIT16_OFFSET 16
#define RX_CSR_51_BIT0_LEN 16
#define RX_CSR_51_BIT0_OFFSET 0

#define RX_CSR_52_BIT16_LEN 16
#define RX_CSR_52_BIT16_OFFSET 16
#define RX_CSR_52_BIT0_LEN 16
#define RX_CSR_52_BIT0_OFFSET 0

#define RX_CSR_53_BIT16_LEN 16
#define RX_CSR_53_BIT16_OFFSET 16
#define RX_CSR_53_BIT0_LEN 16
#define RX_CSR_53_BIT0_OFFSET 0

#define RX_CSR_54_BIT16_LEN 16
#define RX_CSR_54_BIT16_OFFSET 16
#define RX_CSR_54_BIT0_LEN 16
#define RX_CSR_54_BIT0_OFFSET 0

#define RX_CSR_55_BIT16_LEN 16
#define RX_CSR_55_BIT16_OFFSET 16
#define RX_CSR_55_BIT0_LEN 16
#define RX_CSR_55_BIT0_OFFSET 0

#define RX_CSR_56_BIT16_LEN 3
#define RX_CSR_56_BIT16_OFFSET 16
#define RX_CSR_56_BIT0_LEN 16
#define RX_CSR_56_BIT0_OFFSET 0

#define RX_CSR_57_BIT9_LEN 9
#define RX_CSR_57_BIT9_OFFSET 9
#define RX_CSR_57_BIT0_LEN 9
#define RX_CSR_57_BIT0_OFFSET 0

#define RX_CSR_58_BIT16_LEN 16
#define RX_CSR_58_BIT16_OFFSET 16
#define RX_CSR_58_BIT0_LEN 16
#define RX_CSR_58_BIT0_OFFSET 0

#define RX_CSR_59_BIT31_LEN 1
#define RX_CSR_59_BIT31_OFFSET 31
#define RX_CSR_59_BIT30_LEN 1
#define RX_CSR_59_BIT30_OFFSET 30
#define RX_CSR_59_BIT27_LEN 3
#define RX_CSR_59_BIT27_OFFSET 27
#define RX_CSR_59_BIT19_LEN 8
#define RX_CSR_59_BIT19_OFFSET 19
#define RX_CSR_59_BIT11_LEN 8
#define RX_CSR_59_BIT11_OFFSET 11
#define RX_CSR_59_BIT10_LEN 1
#define RX_CSR_59_BIT10_OFFSET 10
#define RX_CSR_59_BIT6_LEN 4
#define RX_CSR_59_BIT6_OFFSET 6
#define RX_CSR_59_BIT4_LEN 2
#define RX_CSR_59_BIT4_OFFSET 4
#define RX_CSR_59_BIT3_LEN 1
#define RX_CSR_59_BIT3_OFFSET 3
#define RX_CSR_59_BIT2_LEN 1
#define RX_CSR_59_BIT2_OFFSET 2
#define RX_CSR_59_BIT1_LEN 1
#define RX_CSR_59_BIT1_OFFSET 1
#define RX_CSR_59_BIT0_LEN 1
#define RX_CSR_59_BIT0_OFFSET 0

#define RX_CSR_60_BIT16_LEN 2
#define RX_CSR_60_BIT16_OFFSET 16
#define RX_CSR_60_BIT14_LEN 1
#define RX_CSR_60_BIT14_OFFSET 14
#define RX_CSR_60_BIT0_LEN 14
#define RX_CSR_60_BIT0_OFFSET 0

#define RX_CSR_61_BIT8_LEN 8
#define RX_CSR_61_BIT8_OFFSET 8
#define RX_CSR_61_BIT0_LEN 8
#define RX_CSR_61_BIT0_OFFSET 0

#define RX_CSR_62_BIT24_LEN 8
#define RX_CSR_62_BIT24_OFFSET 24
#define RX_CSR_62_BIT16_LEN 8
#define RX_CSR_62_BIT16_OFFSET 16
#define RX_CSR_62_BIT8_LEN 8
#define RX_CSR_62_BIT8_OFFSET 8
#define RX_CSR_62_BIT0_LEN 8
#define RX_CSR_62_BIT0_OFFSET 0

#define RX_CSR_63_BIT24_LEN 8
#define RX_CSR_63_BIT24_OFFSET 24
#define RX_CSR_63_BIT16_LEN 8
#define RX_CSR_63_BIT16_OFFSET 16
#define RX_CSR_63_BIT8_LEN 8
#define RX_CSR_63_BIT8_OFFSET 8
#define RX_CSR_63_BIT0_LEN 8
#define RX_CSR_63_BIT0_OFFSET 0

#define RX_CSR_64_BIT24_LEN 8
#define RX_CSR_64_BIT24_OFFSET 24
#define RX_CSR_64_BIT16_LEN 8
#define RX_CSR_64_BIT16_OFFSET 16
#define RX_CSR_64_BIT8_LEN 8
#define RX_CSR_64_BIT8_OFFSET 8
#define RX_CSR_64_BIT0_LEN 8
#define RX_CSR_64_BIT0_OFFSET 0

#define RX_CSR_65_BIT7_LEN 7
#define RX_CSR_65_BIT7_OFFSET 7
#define RX_CSR_65_BIT0_LEN 7
#define RX_CSR_65_BIT0_OFFSET 0

#define RX_CSR_66_BIT21_LEN 7
#define RX_CSR_66_BIT21_OFFSET 21
#define RX_CSR_66_BIT14_LEN 7
#define RX_CSR_66_BIT14_OFFSET 14
#define RX_CSR_66_BIT7_LEN 7
#define RX_CSR_66_BIT7_OFFSET 7
#define RX_CSR_66_BIT0_LEN 7
#define RX_CSR_66_BIT0_OFFSET 0

#define RX_CSR_67_BIT21_LEN 7
#define RX_CSR_67_BIT21_OFFSET 21
#define RX_CSR_67_BIT14_LEN 7
#define RX_CSR_67_BIT14_OFFSET 14
#define RX_CSR_67_BIT7_LEN 7
#define RX_CSR_67_BIT7_OFFSET 7
#define RX_CSR_67_BIT0_LEN 7
#define RX_CSR_67_BIT0_OFFSET 0

#define RX_CSR_68_BIT21_LEN 7
#define RX_CSR_68_BIT21_OFFSET 21
#define RX_CSR_68_BIT14_LEN 7
#define RX_CSR_68_BIT14_OFFSET 14
#define RX_CSR_68_BIT7_LEN 7
#define RX_CSR_68_BIT7_OFFSET 7
#define RX_CSR_68_BIT0_LEN 7
#define RX_CSR_68_BIT0_OFFSET 0

#define RX_CSR_69_BIT8_LEN 8
#define RX_CSR_69_BIT8_OFFSET 8
#define RX_CSR_69_BIT0_LEN 8
#define RX_CSR_69_BIT0_OFFSET 0

#define RX_CSR_70_BIT24_LEN 8
#define RX_CSR_70_BIT24_OFFSET 24
#define RX_CSR_70_BIT16_LEN 8
#define RX_CSR_70_BIT16_OFFSET 16
#define RX_CSR_70_BIT8_LEN 8
#define RX_CSR_70_BIT8_OFFSET 8
#define RX_CSR_70_BIT0_LEN 8
#define RX_CSR_70_BIT0_OFFSET 0

#define RX_CSR_72_BIT9_LEN 1
#define RX_CSR_72_BIT9_OFFSET 9
#define RX_CSR_72_BIT8_LEN 1
#define RX_CSR_72_BIT8_OFFSET 8
#define RX_CSR_72_BIT7_LEN 1
#define RX_CSR_72_BIT7_OFFSET 7
#define RX_CSR_72_BIT6_LEN 1
#define RX_CSR_72_BIT6_OFFSET 6
#define RX_CSR_72_BIT5_LEN 1
#define RX_CSR_72_BIT5_OFFSET 5
#define RX_CSR_72_BIT4_LEN 1
#define RX_CSR_72_BIT4_OFFSET 4
#define RX_CSR_72_BIT3_LEN 1
#define RX_CSR_72_BIT3_OFFSET 3
#define RX_CSR_72_BIT2_LEN 1
#define RX_CSR_72_BIT2_OFFSET 2
#define RX_CSR_72_BIT1_LEN 1
#define RX_CSR_72_BIT1_OFFSET 1
#define RX_CSR_72_BIT0_LEN 1
#define RX_CSR_72_BIT0_OFFSET 0

#define RX_CSR_73_BIT10_LEN 4
#define RX_CSR_73_BIT10_OFFSET 10
#define RX_CSR_73_BIT9_LEN 1
#define RX_CSR_73_BIT9_OFFSET 9
#define RX_CSR_73_BIT8_LEN 1
#define RX_CSR_73_BIT8_OFFSET 8
#define RX_CSR_73_BIT7_LEN 1
#define RX_CSR_73_BIT7_OFFSET 7
#define RX_CSR_73_BIT6_LEN 1
#define RX_CSR_73_BIT6_OFFSET 6
#define RX_CSR_73_BIT5_LEN 1
#define RX_CSR_73_BIT5_OFFSET 5
#define RX_CSR_73_BIT4_LEN 1
#define RX_CSR_73_BIT4_OFFSET 4
#define RX_CSR_73_BIT3_LEN 1
#define RX_CSR_73_BIT3_OFFSET 3
#define RX_CSR_73_BIT2_LEN 1
#define RX_CSR_73_BIT2_OFFSET 2
#define RX_CSR_73_BIT1_LEN 1
#define RX_CSR_73_BIT1_OFFSET 1
#define RX_CSR_73_BIT0_LEN 1
#define RX_CSR_73_BIT0_OFFSET 0

#define RX_CSR_74_BIT9_LEN 1
#define RX_CSR_74_BIT9_OFFSET 9
#define RX_CSR_74_BIT8_LEN 1
#define RX_CSR_74_BIT8_OFFSET 8
#define RX_CSR_74_BIT7_LEN 1
#define RX_CSR_74_BIT7_OFFSET 7
#define RX_CSR_74_BIT6_LEN 1
#define RX_CSR_74_BIT6_OFFSET 6
#define RX_CSR_74_BIT5_LEN 1
#define RX_CSR_74_BIT5_OFFSET 5
#define RX_CSR_74_BIT4_LEN 1
#define RX_CSR_74_BIT4_OFFSET 4
#define RX_CSR_74_BIT3_LEN 1
#define RX_CSR_74_BIT3_OFFSET 3
#define RX_CSR_74_BIT2_LEN 1
#define RX_CSR_74_BIT2_OFFSET 2
#define RX_CSR_74_BIT1_LEN 1
#define RX_CSR_74_BIT1_OFFSET 1
#define RX_CSR_74_BIT0_LEN 1
#define RX_CSR_74_BIT0_OFFSET 0

#define RX_CSR_75_BIT0_LEN 32
#define RX_CSR_75_BIT0_OFFSET 0

#define RX_CSR_76_BIT0_LEN 32
#define RX_CSR_76_BIT0_OFFSET 0

#define RX_CSR_80_BIT0_LEN 8
#define RX_CSR_80_BIT0_OFFSET 0

#define RX_CSR_81_BIT27_LEN 1
#define RX_CSR_81_BIT27_OFFSET 27
#define RX_CSR_81_BIT26_LEN 1
#define RX_CSR_81_BIT26_OFFSET 26
#define RX_CSR_81_BIT25_LEN 1
#define RX_CSR_81_BIT25_OFFSET 25
#define RX_CSR_81_BIT24_LEN 1
#define RX_CSR_81_BIT24_OFFSET 24
#define RX_CSR_81_BIT23_LEN 1
#define RX_CSR_81_BIT23_OFFSET 23
#define RX_CSR_81_BIT22_LEN 1
#define RX_CSR_81_BIT22_OFFSET 22
#define RX_CSR_81_BIT21_LEN 1
#define RX_CSR_81_BIT21_OFFSET 21
#define RX_CSR_81_BIT20_LEN 1
#define RX_CSR_81_BIT20_OFFSET 20
#define RX_CSR_81_BIT19_LEN 1
#define RX_CSR_81_BIT19_OFFSET 19
#define RX_CSR_81_BIT18_LEN 1
#define RX_CSR_81_BIT18_OFFSET 18
#define RX_CSR_81_BIT17_LEN 1
#define RX_CSR_81_BIT17_OFFSET 17
#define RX_CSR_81_BIT16_LEN 1
#define RX_CSR_81_BIT16_OFFSET 16
#define RX_CSR_81_BIT15_LEN 1
#define RX_CSR_81_BIT15_OFFSET 15
#define RX_CSR_81_BIT14_LEN 1
#define RX_CSR_81_BIT14_OFFSET 14
#define RX_CSR_81_BIT13_LEN 1
#define RX_CSR_81_BIT13_OFFSET 13
#define RX_CSR_81_BIT12_LEN 1
#define RX_CSR_81_BIT12_OFFSET 12
#define RX_CSR_81_BIT11_LEN 1
#define RX_CSR_81_BIT11_OFFSET 11
#define RX_CSR_81_BIT10_LEN 1
#define RX_CSR_81_BIT10_OFFSET 10
#define RX_CSR_81_BIT9_LEN 1
#define RX_CSR_81_BIT9_OFFSET 9
#define RX_CSR_81_BIT8_LEN 1
#define RX_CSR_81_BIT8_OFFSET 8
#define RX_CSR_81_BIT7_LEN 1
#define RX_CSR_81_BIT7_OFFSET 7
#define RX_CSR_81_BIT6_LEN 1
#define RX_CSR_81_BIT6_OFFSET 6
#define RX_CSR_81_BIT5_LEN 1
#define RX_CSR_81_BIT5_OFFSET 5
#define RX_CSR_81_BIT4_LEN 1
#define RX_CSR_81_BIT4_OFFSET 4
#define RX_CSR_81_BIT3_LEN 1
#define RX_CSR_81_BIT3_OFFSET 3
#define RX_CSR_81_BIT2_LEN 1
#define RX_CSR_81_BIT2_OFFSET 2
#define RX_CSR_81_BIT1_LEN 1
#define RX_CSR_81_BIT1_OFFSET 1
#define RX_CSR_81_BIT0_LEN 1
#define RX_CSR_81_BIT0_OFFSET 0

#define RX_CSR_82_BIT20_LEN 1
#define RX_CSR_82_BIT20_OFFSET 20
#define RX_CSR_82_BIT19_LEN 1
#define RX_CSR_82_BIT19_OFFSET 19
#define RX_CSR_82_BIT18_LEN 1
#define RX_CSR_82_BIT18_OFFSET 18
#define RX_CSR_82_BIT17_LEN 1
#define RX_CSR_82_BIT17_OFFSET 17
#define RX_CSR_82_BIT16_LEN 1
#define RX_CSR_82_BIT16_OFFSET 16
#define RX_CSR_82_BIT15_LEN 1
#define RX_CSR_82_BIT15_OFFSET 15
#define RX_CSR_82_BIT14_LEN 1
#define RX_CSR_82_BIT14_OFFSET 14
#define RX_CSR_82_BIT13_LEN 1
#define RX_CSR_82_BIT13_OFFSET 13
#define RX_CSR_82_BIT12_LEN 1
#define RX_CSR_82_BIT12_OFFSET 12
#define RX_CSR_82_BIT11_LEN 1
#define RX_CSR_82_BIT11_OFFSET 11
#define RX_CSR_82_BIT10_LEN 1
#define RX_CSR_82_BIT10_OFFSET 10
#define RX_CSR_82_BIT9_LEN 1
#define RX_CSR_82_BIT9_OFFSET 9
#define RX_CSR_82_BIT8_LEN 1
#define RX_CSR_82_BIT8_OFFSET 8
#define RX_CSR_82_BIT7_LEN 1
#define RX_CSR_82_BIT7_OFFSET 7
#define RX_CSR_82_BIT6_LEN 1
#define RX_CSR_82_BIT6_OFFSET 6
#define RX_CSR_82_BIT5_LEN 1
#define RX_CSR_82_BIT5_OFFSET 5
#define RX_CSR_82_BIT4_LEN 1
#define RX_CSR_82_BIT4_OFFSET 4
#define RX_CSR_82_BIT3_LEN 1
#define RX_CSR_82_BIT3_OFFSET 3
#define RX_CSR_82_BIT2_LEN 1
#define RX_CSR_82_BIT2_OFFSET 2
#define RX_CSR_82_BIT1_LEN 1
#define RX_CSR_82_BIT1_OFFSET 1
#define RX_CSR_82_BIT0_LEN 1
#define RX_CSR_82_BIT0_OFFSET 0

#define RX_CSR_83_BIT23_LEN 1
#define RX_CSR_83_BIT23_OFFSET 23
#define RX_CSR_83_BIT22_LEN 1
#define RX_CSR_83_BIT22_OFFSET 22
#define RX_CSR_83_BIT21_LEN 1
#define RX_CSR_83_BIT21_OFFSET 21
#define RX_CSR_83_BIT20_LEN 1
#define RX_CSR_83_BIT20_OFFSET 20
#define RX_CSR_83_BIT19_LEN 1
#define RX_CSR_83_BIT19_OFFSET 19
#define RX_CSR_83_BIT18_LEN 1
#define RX_CSR_83_BIT18_OFFSET 18
#define RX_CSR_83_BIT17_LEN 1
#define RX_CSR_83_BIT17_OFFSET 17
#define RX_CSR_83_BIT16_LEN 1
#define RX_CSR_83_BIT16_OFFSET 16
#define RX_CSR_83_BIT15_LEN 1
#define RX_CSR_83_BIT15_OFFSET 15
#define RX_CSR_83_BIT14_LEN 1
#define RX_CSR_83_BIT14_OFFSET 14
#define RX_CSR_83_BIT13_LEN 1
#define RX_CSR_83_BIT13_OFFSET 13
#define RX_CSR_83_BIT12_LEN 1
#define RX_CSR_83_BIT12_OFFSET 12
#define RX_CSR_83_BIT11_LEN 1
#define RX_CSR_83_BIT11_OFFSET 11
#define RX_CSR_83_BIT10_LEN 1
#define RX_CSR_83_BIT10_OFFSET 10
#define RX_CSR_83_BIT9_LEN 1
#define RX_CSR_83_BIT9_OFFSET 9
#define RX_CSR_83_BIT8_LEN 1
#define RX_CSR_83_BIT8_OFFSET 8
#define RX_CSR_83_BIT7_LEN 1
#define RX_CSR_83_BIT7_OFFSET 7
#define RX_CSR_83_BIT6_LEN 1
#define RX_CSR_83_BIT6_OFFSET 6
#define RX_CSR_83_BIT5_LEN 1
#define RX_CSR_83_BIT5_OFFSET 5
#define RX_CSR_83_BIT4_LEN 1
#define RX_CSR_83_BIT4_OFFSET 4
#define RX_CSR_83_BIT3_LEN 1
#define RX_CSR_83_BIT3_OFFSET 3
#define RX_CSR_83_BIT2_LEN 1
#define RX_CSR_83_BIT2_OFFSET 2
#define RX_CSR_83_BIT1_LEN 1
#define RX_CSR_83_BIT1_OFFSET 1
#define RX_CSR_83_BIT0_LEN 1
#define RX_CSR_83_BIT0_OFFSET 0

#define RX_CSR_84_BIT13_LEN 1
#define RX_CSR_84_BIT13_OFFSET 13
#define RX_CSR_84_BIT12_LEN 1
#define RX_CSR_84_BIT12_OFFSET 12
#define RX_CSR_84_BIT11_LEN 1
#define RX_CSR_84_BIT11_OFFSET 11
#define RX_CSR_84_BIT10_LEN 1
#define RX_CSR_84_BIT10_OFFSET 10
#define RX_CSR_84_BIT9_LEN 1
#define RX_CSR_84_BIT9_OFFSET 9
#define RX_CSR_84_BIT8_LEN 1
#define RX_CSR_84_BIT8_OFFSET 8
#define RX_CSR_84_BIT7_LEN 1
#define RX_CSR_84_BIT7_OFFSET 7
#define RX_CSR_84_BIT6_LEN 1
#define RX_CSR_84_BIT6_OFFSET 6
#define RX_CSR_84_BIT5_LEN 1
#define RX_CSR_84_BIT5_OFFSET 5
#define RX_CSR_84_BIT4_LEN 1
#define RX_CSR_84_BIT4_OFFSET 4
#define RX_CSR_84_BIT3_LEN 1
#define RX_CSR_84_BIT3_OFFSET 3
#define RX_CSR_84_BIT2_LEN 1
#define RX_CSR_84_BIT2_OFFSET 2
#define RX_CSR_84_BIT1_LEN 1
#define RX_CSR_84_BIT1_OFFSET 1
#define RX_CSR_84_BIT0_LEN 1
#define RX_CSR_84_BIT0_OFFSET 0

#define RX_CSR_85_BIT23_LEN 1
#define RX_CSR_85_BIT23_OFFSET 23
#define RX_CSR_85_BIT22_LEN 1
#define RX_CSR_85_BIT22_OFFSET 22
#define RX_CSR_85_BIT21_LEN 1
#define RX_CSR_85_BIT21_OFFSET 21
#define RX_CSR_85_BIT20_LEN 1
#define RX_CSR_85_BIT20_OFFSET 20
#define RX_CSR_85_BIT19_LEN 1
#define RX_CSR_85_BIT19_OFFSET 19
#define RX_CSR_85_BIT18_LEN 1
#define RX_CSR_85_BIT18_OFFSET 18
#define RX_CSR_85_BIT17_LEN 1
#define RX_CSR_85_BIT17_OFFSET 17
#define RX_CSR_85_BIT16_LEN 1
#define RX_CSR_85_BIT16_OFFSET 16
#define RX_CSR_85_BIT15_LEN 1
#define RX_CSR_85_BIT15_OFFSET 15
#define RX_CSR_85_BIT14_LEN 1
#define RX_CSR_85_BIT14_OFFSET 14
#define RX_CSR_85_BIT13_LEN 1
#define RX_CSR_85_BIT13_OFFSET 13
#define RX_CSR_85_BIT12_LEN 1
#define RX_CSR_85_BIT12_OFFSET 12
#define RX_CSR_85_BIT11_LEN 1
#define RX_CSR_85_BIT11_OFFSET 11
#define RX_CSR_85_BIT10_LEN 1
#define RX_CSR_85_BIT10_OFFSET 10
#define RX_CSR_85_BIT9_LEN 1
#define RX_CSR_85_BIT9_OFFSET 9
#define RX_CSR_85_BIT8_LEN 1
#define RX_CSR_85_BIT8_OFFSET 8
#define RX_CSR_85_BIT7_LEN 1
#define RX_CSR_85_BIT7_OFFSET 7
#define RX_CSR_85_BIT6_LEN 1
#define RX_CSR_85_BIT6_OFFSET 6
#define RX_CSR_85_BIT5_LEN 1
#define RX_CSR_85_BIT5_OFFSET 5
#define RX_CSR_85_BIT4_LEN 1
#define RX_CSR_85_BIT4_OFFSET 4
#define RX_CSR_85_BIT3_LEN 1
#define RX_CSR_85_BIT3_OFFSET 3
#define RX_CSR_85_BIT2_LEN 1
#define RX_CSR_85_BIT2_OFFSET 2
#define RX_CSR_85_BIT1_LEN 1
#define RX_CSR_85_BIT1_OFFSET 1
#define RX_CSR_85_BIT0_LEN 1
#define RX_CSR_85_BIT0_OFFSET 0

#define RX_CSR_86_BIT27_LEN 5
#define RX_CSR_86_BIT27_OFFSET 27
#define RX_CSR_86_BIT25_LEN 2
#define RX_CSR_86_BIT25_OFFSET 25
#define RX_CSR_86_BIT22_LEN 3
#define RX_CSR_86_BIT22_OFFSET 22
#define RX_CSR_86_BIT21_LEN 1
#define RX_CSR_86_BIT21_OFFSET 21
#define RX_CSR_86_BIT19_LEN 2
#define RX_CSR_86_BIT19_OFFSET 19
#define RX_CSR_86_BIT18_LEN 1
#define RX_CSR_86_BIT18_OFFSET 18
#define RX_CSR_86_BIT16_LEN 2
#define RX_CSR_86_BIT16_OFFSET 16
#define RX_CSR_86_BIT14_LEN 2
#define RX_CSR_86_BIT14_OFFSET 14
#define RX_CSR_86_BIT11_LEN 3
#define RX_CSR_86_BIT11_OFFSET 11
#define RX_CSR_86_BIT6_LEN 5
#define RX_CSR_86_BIT6_OFFSET 6
#define RX_CSR_86_BIT4_LEN 2
#define RX_CSR_86_BIT4_OFFSET 4
#define RX_CSR_86_BIT0_LEN 4
#define RX_CSR_86_BIT0_OFFSET 0

#define RX_CSR_87_BIT25_LEN 1
#define RX_CSR_87_BIT25_OFFSET 25
#define RX_CSR_87_BIT24_LEN 1
#define RX_CSR_87_BIT24_OFFSET 24
#define RX_CSR_87_BIT22_LEN 2
#define RX_CSR_87_BIT22_OFFSET 22
#define RX_CSR_87_BIT20_LEN 2
#define RX_CSR_87_BIT20_OFFSET 20
#define RX_CSR_87_BIT18_LEN 2
#define RX_CSR_87_BIT18_OFFSET 18
#define RX_CSR_87_BIT14_LEN 4
#define RX_CSR_87_BIT14_OFFSET 14
#define RX_CSR_87_BIT10_LEN 4
#define RX_CSR_87_BIT10_OFFSET 10
#define RX_CSR_87_BIT6_LEN 4
#define RX_CSR_87_BIT6_OFFSET 6
#define RX_CSR_87_BIT2_LEN 4
#define RX_CSR_87_BIT2_OFFSET 2
#define RX_CSR_87_BIT1_LEN 1
#define RX_CSR_87_BIT1_OFFSET 1
#define RX_CSR_87_BIT0_LEN 1
#define RX_CSR_87_BIT0_OFFSET 0

#define RX_CSR_88_BIT22_LEN 1
#define RX_CSR_88_BIT22_OFFSET 22
#define RX_CSR_88_BIT21_LEN 1
#define RX_CSR_88_BIT21_OFFSET 21
#define RX_CSR_88_BIT17_LEN 4
#define RX_CSR_88_BIT17_OFFSET 17
#define RX_CSR_88_BIT15_LEN 2
#define RX_CSR_88_BIT15_OFFSET 15
#define RX_CSR_88_BIT12_LEN 3
#define RX_CSR_88_BIT12_OFFSET 12
#define RX_CSR_88_BIT4_LEN 1
#define RX_CSR_88_BIT4_OFFSET 4
#define RX_CSR_88_BIT3_LEN 1
#define RX_CSR_88_BIT3_OFFSET 3
#define RX_CSR_88_BIT2_LEN 1
#define RX_CSR_88_BIT2_OFFSET 2
#define RX_CSR_88_BIT1_LEN 1
#define RX_CSR_88_BIT1_OFFSET 1
#define RX_CSR_88_BIT0_LEN 1
#define RX_CSR_88_BIT0_OFFSET 0

#define RX_CSR_89_BIT27_LEN 1
#define RX_CSR_89_BIT27_OFFSET 27
#define RX_CSR_89_BIT24_LEN 3
#define RX_CSR_89_BIT24_OFFSET 24
#define RX_CSR_89_BIT20_LEN 4
#define RX_CSR_89_BIT20_OFFSET 20
#define RX_CSR_89_BIT19_LEN 1
#define RX_CSR_89_BIT19_OFFSET 19
#define RX_CSR_89_BIT18_LEN 1
#define RX_CSR_89_BIT18_OFFSET 18
#define RX_CSR_89_BIT17_LEN 1
#define RX_CSR_89_BIT17_OFFSET 17
#define RX_CSR_89_BIT16_LEN 1
#define RX_CSR_89_BIT16_OFFSET 16
#define RX_CSR_89_BIT12_LEN 4
#define RX_CSR_89_BIT12_OFFSET 12
#define RX_CSR_89_BIT8_LEN 4
#define RX_CSR_89_BIT8_OFFSET 8
#define RX_CSR_89_BIT5_LEN 1
#define RX_CSR_89_BIT5_OFFSET 5
#define RX_CSR_89_BIT4_LEN 1
#define RX_CSR_89_BIT4_OFFSET 4
#define RX_CSR_89_BIT3_LEN 1
#define RX_CSR_89_BIT3_OFFSET 3
#define RX_CSR_89_BIT2_LEN 1
#define RX_CSR_89_BIT2_OFFSET 2
#define RX_CSR_89_BIT1_LEN 1
#define RX_CSR_89_BIT1_OFFSET 1
#define RX_CSR_89_BIT0_LEN 1
#define RX_CSR_89_BIT0_OFFSET 0

#define RX_CSR_90_BIT25_LEN 4
#define RX_CSR_90_BIT25_OFFSET 25
#define RX_CSR_90_BIT22_LEN 3
#define RX_CSR_90_BIT22_OFFSET 22
#define RX_CSR_90_BIT21_LEN 1
#define RX_CSR_90_BIT21_OFFSET 21
#define RX_CSR_90_BIT17_LEN 4
#define RX_CSR_90_BIT17_OFFSET 17
#define RX_CSR_90_BIT14_LEN 3
#define RX_CSR_90_BIT14_OFFSET 14
#define RX_CSR_90_BIT9_LEN 5
#define RX_CSR_90_BIT9_OFFSET 9
#define RX_CSR_90_BIT5_LEN 4
#define RX_CSR_90_BIT5_OFFSET 5
#define RX_CSR_90_BIT1_LEN 4
#define RX_CSR_90_BIT1_OFFSET 1
#define RX_CSR_90_BIT0_LEN 1
#define RX_CSR_90_BIT0_OFFSET 0

#define RX_CSR_91_BIT26_LEN 3
#define RX_CSR_91_BIT26_OFFSET 26
#define RX_CSR_91_BIT22_LEN 4
#define RX_CSR_91_BIT22_OFFSET 22
#define RX_CSR_91_BIT19_LEN 3
#define RX_CSR_91_BIT19_OFFSET 19
#define RX_CSR_91_BIT14_LEN 5
#define RX_CSR_91_BIT14_OFFSET 14
#define RX_CSR_91_BIT10_LEN 4
#define RX_CSR_91_BIT10_OFFSET 10
#define RX_CSR_91_BIT6_LEN 4
#define RX_CSR_91_BIT6_OFFSET 6
#define RX_CSR_91_BIT3_LEN 3
#define RX_CSR_91_BIT3_OFFSET 3
#define RX_CSR_91_BIT0_LEN 3
#define RX_CSR_91_BIT0_OFFSET 0

#define RX_CSR_92_BIT27_LEN 1
#define RX_CSR_92_BIT27_OFFSET 27
#define RX_CSR_92_BIT26_LEN 1
#define RX_CSR_92_BIT26_OFFSET 26
#define RX_CSR_92_BIT22_LEN 4
#define RX_CSR_92_BIT22_OFFSET 22
#define RX_CSR_92_BIT19_LEN 3
#define RX_CSR_92_BIT19_OFFSET 19
#define RX_CSR_92_BIT18_LEN 1
#define RX_CSR_92_BIT18_OFFSET 18
#define RX_CSR_92_BIT15_LEN 3
#define RX_CSR_92_BIT15_OFFSET 15
#define RX_CSR_92_BIT12_LEN 3
#define RX_CSR_92_BIT12_OFFSET 12
#define RX_CSR_92_BIT9_LEN 3
#define RX_CSR_92_BIT9_OFFSET 9
#define RX_CSR_92_BIT8_LEN 1
#define RX_CSR_92_BIT8_OFFSET 8
#define RX_CSR_92_BIT5_LEN 3
#define RX_CSR_92_BIT5_OFFSET 5
#define RX_CSR_92_BIT0_LEN 5
#define RX_CSR_92_BIT0_OFFSET 0

#define RX_CSR_93_BIT23_LEN 7
#define RX_CSR_93_BIT23_OFFSET 23
#define RX_CSR_93_BIT16_LEN 7
#define RX_CSR_93_BIT16_OFFSET 16
#define RX_CSR_93_BIT7_LEN 7
#define RX_CSR_93_BIT7_OFFSET 7
#define RX_CSR_93_BIT0_LEN 7
#define RX_CSR_93_BIT0_OFFSET 0

#define RX_CSR_94_BIT23_LEN 7
#define RX_CSR_94_BIT23_OFFSET 23
#define RX_CSR_94_BIT16_LEN 7
#define RX_CSR_94_BIT16_OFFSET 16
#define RX_CSR_94_BIT7_LEN 7
#define RX_CSR_94_BIT7_OFFSET 7
#define RX_CSR_94_BIT0_LEN 7
#define RX_CSR_94_BIT0_OFFSET 0

#define RX_CSR_95_BIT23_LEN 7
#define RX_CSR_95_BIT23_OFFSET 23
#define RX_CSR_95_BIT16_LEN 7
#define RX_CSR_95_BIT16_OFFSET 16
#define RX_CSR_95_BIT7_LEN 7
#define RX_CSR_95_BIT7_OFFSET 7
#define RX_CSR_95_BIT0_LEN 7
#define RX_CSR_95_BIT0_OFFSET 0

#define RX_CSR_96_BIT23_LEN 7
#define RX_CSR_96_BIT23_OFFSET 23
#define RX_CSR_96_BIT16_LEN 7
#define RX_CSR_96_BIT16_OFFSET 16
#define RX_CSR_96_BIT7_LEN 7
#define RX_CSR_96_BIT7_OFFSET 7
#define RX_CSR_96_BIT0_LEN 7
#define RX_CSR_96_BIT0_OFFSET 0

#define RX_CSR_97_BIT23_LEN 7
#define RX_CSR_97_BIT23_OFFSET 23
#define RX_CSR_97_BIT16_LEN 7
#define RX_CSR_97_BIT16_OFFSET 16
#define RX_CSR_97_BIT7_LEN 7
#define RX_CSR_97_BIT7_OFFSET 7
#define RX_CSR_97_BIT0_LEN 7
#define RX_CSR_97_BIT0_OFFSET 0

#define RX_CSR_98_BIT23_LEN 7
#define RX_CSR_98_BIT23_OFFSET 23
#define RX_CSR_98_BIT16_LEN 7
#define RX_CSR_98_BIT16_OFFSET 16
#define RX_CSR_98_BIT7_LEN 7
#define RX_CSR_98_BIT7_OFFSET 7
#define RX_CSR_98_BIT0_LEN 7
#define RX_CSR_98_BIT0_OFFSET 0

#define RX_CSR_99_BIT23_LEN 7
#define RX_CSR_99_BIT23_OFFSET 23
#define RX_CSR_99_BIT16_LEN 7
#define RX_CSR_99_BIT16_OFFSET 16
#define RX_CSR_99_BIT7_LEN 7
#define RX_CSR_99_BIT7_OFFSET 7
#define RX_CSR_99_BIT0_LEN 7
#define RX_CSR_99_BIT0_OFFSET 0

#define RX_CSR_100_BIT24_LEN 8
#define RX_CSR_100_BIT24_OFFSET 24
#define RX_CSR_100_BIT16_LEN 8
#define RX_CSR_100_BIT16_OFFSET 16
#define RX_CSR_100_BIT8_LEN 8
#define RX_CSR_100_BIT8_OFFSET 8
#define RX_CSR_100_BIT0_LEN 8
#define RX_CSR_100_BIT0_OFFSET 0

#define RX_CSR_101_BIT24_LEN 8
#define RX_CSR_101_BIT24_OFFSET 24
#define RX_CSR_101_BIT16_LEN 8
#define RX_CSR_101_BIT16_OFFSET 16
#define RX_CSR_101_BIT8_LEN 8
#define RX_CSR_101_BIT8_OFFSET 8
#define RX_CSR_101_BIT0_LEN 8
#define RX_CSR_101_BIT0_OFFSET 0

#define RX_CSR_102_BIT23_LEN 1
#define RX_CSR_102_BIT23_OFFSET 23
#define RX_CSR_102_BIT22_LEN 1
#define RX_CSR_102_BIT22_OFFSET 22
#define RX_CSR_102_BIT20_LEN 2
#define RX_CSR_102_BIT20_OFFSET 20
#define RX_CSR_102_BIT10_LEN 3
#define RX_CSR_102_BIT10_OFFSET 10
#define RX_CSR_102_BIT7_LEN 3
#define RX_CSR_102_BIT7_OFFSET 7
#define RX_CSR_102_BIT4_LEN 3
#define RX_CSR_102_BIT4_OFFSET 4
#define RX_CSR_102_BIT1_LEN 3
#define RX_CSR_102_BIT1_OFFSET 1
#define RX_CSR_102_BIT0_LEN 1
#define RX_CSR_102_BIT0_OFFSET 0

#define RX_CSR_103_BIT27_LEN 5
#define RX_CSR_103_BIT27_OFFSET 27
#define RX_CSR_103_BIT22_LEN 5
#define RX_CSR_103_BIT22_OFFSET 22
#define RX_CSR_103_BIT18_LEN 4
#define RX_CSR_103_BIT18_OFFSET 18
#define RX_CSR_103_BIT15_LEN 3
#define RX_CSR_103_BIT15_OFFSET 15
#define RX_CSR_103_BIT12_LEN 3
#define RX_CSR_103_BIT12_OFFSET 12
#define RX_CSR_103_BIT9_LEN 3
#define RX_CSR_103_BIT9_OFFSET 9
#define RX_CSR_103_BIT6_LEN 3
#define RX_CSR_103_BIT6_OFFSET 6
#define RX_CSR_103_BIT3_LEN 3
#define RX_CSR_103_BIT3_OFFSET 3
#define RX_CSR_103_BIT0_LEN 3
#define RX_CSR_103_BIT0_OFFSET 0

#define RX_CSR_104_BIT18_LEN 2
#define RX_CSR_104_BIT18_OFFSET 18
#define RX_CSR_104_BIT17_LEN 1
#define RX_CSR_104_BIT17_OFFSET 17
#define RX_CSR_104_BIT13_LEN 4
#define RX_CSR_104_BIT13_OFFSET 13
#define RX_CSR_104_BIT12_LEN 1
#define RX_CSR_104_BIT12_OFFSET 12
#define RX_CSR_104_BIT11_LEN 1
#define RX_CSR_104_BIT11_OFFSET 11
#define RX_CSR_104_BIT7_LEN 4
#define RX_CSR_104_BIT7_OFFSET 7
#define RX_CSR_104_BIT6_LEN 1
#define RX_CSR_104_BIT6_OFFSET 6
#define RX_CSR_104_BIT1_LEN 5
#define RX_CSR_104_BIT1_OFFSET 1
#define RX_CSR_104_BIT0_LEN 1
#define RX_CSR_104_BIT0_OFFSET 0

#define RX_CSR_105_BIT27_LEN 4
#define RX_CSR_105_BIT27_OFFSET 27
#define RX_CSR_105_BIT23_LEN 4
#define RX_CSR_105_BIT23_OFFSET 23
#define RX_CSR_105_BIT19_LEN 4
#define RX_CSR_105_BIT19_OFFSET 19
#define RX_CSR_105_BIT15_LEN 4
#define RX_CSR_105_BIT15_OFFSET 15
#define RX_CSR_105_BIT14_LEN 1
#define RX_CSR_105_BIT14_OFFSET 14
#define RX_CSR_105_BIT12_LEN 2
#define RX_CSR_105_BIT12_OFFSET 12
#define RX_CSR_105_BIT11_LEN 1
#define RX_CSR_105_BIT11_OFFSET 11
#define RX_CSR_105_BIT5_LEN 1
#define RX_CSR_105_BIT5_OFFSET 5
#define RX_CSR_105_BIT4_LEN 1
#define RX_CSR_105_BIT4_OFFSET 4
#define RX_CSR_105_BIT3_LEN 1
#define RX_CSR_105_BIT3_OFFSET 3
#define RX_CSR_105_BIT2_LEN 1
#define RX_CSR_105_BIT2_OFFSET 2
#define RX_CSR_105_BIT1_LEN 1
#define RX_CSR_105_BIT1_OFFSET 1
#define RX_CSR_105_BIT0_LEN 1
#define RX_CSR_105_BIT0_OFFSET 0

#define RX_CSR_106_BIT21_LEN 1
#define RX_CSR_106_BIT21_OFFSET 21
#define RX_CSR_106_BIT20_LEN 1
#define RX_CSR_106_BIT20_OFFSET 20
#define RX_CSR_106_BIT19_LEN 1
#define RX_CSR_106_BIT19_OFFSET 19
#define RX_CSR_106_BIT17_LEN 2
#define RX_CSR_106_BIT17_OFFSET 17
#define RX_CSR_106_BIT15_LEN 2
#define RX_CSR_106_BIT15_OFFSET 15
#define RX_CSR_106_BIT10_LEN 5
#define RX_CSR_106_BIT10_OFFSET 10
#define RX_CSR_106_BIT7_LEN 3
#define RX_CSR_106_BIT7_OFFSET 7
#define RX_CSR_106_BIT6_LEN 1
#define RX_CSR_106_BIT6_OFFSET 6
#define RX_CSR_106_BIT0_LEN 6
#define RX_CSR_106_BIT0_OFFSET 0

#define RX_CSR_107_BIT23_LEN 1
#define RX_CSR_107_BIT23_OFFSET 23
#define RX_CSR_107_BIT17_LEN 6
#define RX_CSR_107_BIT17_OFFSET 17
#define RX_CSR_107_BIT13_LEN 4
#define RX_CSR_107_BIT13_OFFSET 13
#define RX_CSR_107_BIT9_LEN 4
#define RX_CSR_107_BIT9_OFFSET 9
#define RX_CSR_107_BIT7_LEN 2
#define RX_CSR_107_BIT7_OFFSET 7
#define RX_CSR_107_BIT6_LEN 1
#define RX_CSR_107_BIT6_OFFSET 6
#define RX_CSR_107_BIT5_LEN 1
#define RX_CSR_107_BIT5_OFFSET 5
#define RX_CSR_107_BIT4_LEN 1
#define RX_CSR_107_BIT4_OFFSET 4
#define RX_CSR_107_BIT3_LEN 1
#define RX_CSR_107_BIT3_OFFSET 3
#define RX_CSR_107_BIT2_LEN 1
#define RX_CSR_107_BIT2_OFFSET 2
#define RX_CSR_107_BIT1_LEN 1
#define RX_CSR_107_BIT1_OFFSET 1
#define RX_CSR_107_BIT0_LEN 1
#define RX_CSR_107_BIT0_OFFSET 0

#endif // __RX_CSR_REG_OFFSET_FIELD_H__
